This invention relates to semiconductor capacitors and more particularly to a system and method for forming high dielectric constant decoupling capacitors for semiconductor structures.
Materials having a high dielectric constant are particularly well suited for use in decoupling capacitors. High dielectric constant materials include ferroelectrics, relaxors, paraelectrics, perovskites, pyrochlores, layered perovskites or any material with a dielectric constant which is greater than or equal to 20. Examples of such materials include Ta2O5, BaTiO3, SrTiO3, BaStTiO3 (BST or BSTO), PbZrTiO3 (PZT), PbZrO3, PbLaTiO3 (PLT), and SrBiTiO3 (SBT).
Ferroelectric decoupling capacitors utilize the ferroelectric effect, which is the tendency of small electrically asymmetric elements, called dipoles, to spontaneously polarize, or align in parallel, within certain crystals when under the influence of an externally applied electric field. The elements remain polarized after the electric field is removed. However, when a reverse electric field is applied, the reverse electric field causes spontaneous polarization (i.e., alignment of the dipoles) in the opposite direction. Thus, ferroelectric materials have two stable polarization states, and can be utilized in bistable capacitors having two distinct polarization voltage thresholds. Since no external electric field or current is required for the ferroelectric material to remain polarized in either state, a capacitor can be fabricated which can store charges without requiring power to retain the stored charges.
Ferroelectric (FE) films that are used as storage elements have relative dielectric constants which are a few orders of magnitude higher than that of silicon dioxide (e.g., 1000-1500 versus 3.8-7.0 for typical DRAM capacitors). Thus a thicker film can be used to provide high capacitance. Lead zirconate titanate (PZT) has been most commonly used and studied. A ferroelectric capacitor using lead zirconate titanate (PZT) film can store a large charge, e.g., 10 uC/cm2, compared to an equivalent sized SiO2 capacitor that may store only 0.1 uC/cm2. Ferroelectric films such as PZT remain ferroelectric from xe2x88x9280 to +350xc2x0 C., which is a range well beyond the operating temperature of existing silicon devices. Also, the processing requirements for a PZT ferroelectric capacitor are compatible with conventional semiconductor wafer processing techniques and semiconductor packaging processing techniques.
The earliest ferroelectric thin film was made of potassium nitrate and lead zirconate titanate (PZT). The storage capacitor was constructed from two metal electrodes thin FE film inserted between the metallization layers. High dielectric constant materials, such as Ta2O5, have been used in the packages as discrete devices for decoupling purposes. FIG. 1 shows a typical hysteresis I-V switching loop for the PZT film and operating characteristics. For positive voltages greater than the coercive voltage (Vc) applied to the ferroelectric capacitor, the film is polarized in the positive direction to a saturation value of Ps. The coercive voltage (Vc) is defined as the value where polarization reverses and the curve crosses the X-axis. On removal of the applied voltage, the polarization relaxes to a value Pr called the remnant polarization. On the application of negative voltage to the ferroelectric film, the resulting polarization is in the negative direction, reaching a saturation value of xe2x88x92Ps and a remnant (or relaxed) polarization of xe2x88x92Pr.
For a ferroelectric capacitor, once the capacitor is charged during the initial operation or the burn-in process with a voltage higher than Vr, the capacitor will remain at a capacitance value near the maximum capacitance even when the power supply is removed. To change the direction of this polarization, a negative voltage greater than xe2x88x92Vr has to be applied to reverse the polarization. Thus, the decoupling effect of the capacitor can be maintained even when no power is being supplied to the device. This can effectively negate any transient noise which would otherwise be encountered during the onset of the power supply.
As described in the prior art, (see: e.g., xe2x80x9cPreparation and properties of sol-gel derived PZT thin films for decoupling capacitor applicationxe2x80x9d, Schwartz, R. W. Dimes, D. Lockwood, S. J. Torres, V. M., Integrated Ferroelectrics v.4 no.2 March 1994, pp.165-174; and xe2x80x9cElectrical properties of sol-gel PZT thin films for decoupling capacitor applicationsxe2x80x9d, Schwartz, Robert W. Dimos, D. Lockwood, S. J. Torres, V. M., Ferroelectric Thin Films III Materials Research Society Symposium Proceedings v.310, 1993. pp.59-64), ferroelectric material capacitors have been used in packaging where noise has been a more serious problem. However, as the more recent chip technology pushes into higher speed, denser interconnects, and larger chip area, the noise in the power supply lines due to circuit switching becomes a common problem for the chip applications. It is proposed that, by adding decoupling capacitors on the chip, located in close proximity to the circuit, one can effectively reduce the power supply noise. In order to limit the surge of noise to a desired level, the value of the decoupling capacitance is typically 5 times that of the line loading capacitance.
Two alternative prior art on-chip capacitors are illustrated in FIGS. 2A and 2B. FIG. 2A illustrates a planar capacitor which uses the gate dielectric 201 between the gate electrode 202, which is connected to the voltage source and acts as the plate node, and the source and drain regions 203 and 204 in n-type substrate 205 over a p-type well, wherein the source and drain regions are connected to ground as the ground node. FIG. 2B illustrates an alternative on-chip capacitor which uses the DRAM deep trench dielectric for storing charges. The transfer gate 212 connected to the voltage source serves as the plate node with trench material 222, while the n+ region surrounding the trench is the ground node, with the trench dielectric 211 storing the charges between the two. While prior art on-chip capacitors have been fabricated, the former embodiment of FIG. 2A relies on the gate dielectric which is generally an oxide having a relatively low dielectric constant, and is therefore, not a terribly effective capacitor. The latter embodiment of FIG. 2B also relies on the existing dielectric material with its low dielectric constant and is more costly in terms of substrate real estate and processing complexity.
What is desired, and what is an object of the present invention, therefore, is to provide a compact size, high capacitance value, reliable decoupling capacitor using ferroelectric material, which capacitor can be integrated into the silicon interconnect process for semiconductor packaging and for on-chip applications with minimum added cost.
The foregoing and other objects of the invention are realized by the present invention which provides ferroelectric decoupling capacitors on the semiconductor chip and on semiconductor chip packaging. The ferroelectric decoupling capacitor can be fabricated between adjacent lines on the same level, between lines of successive levels, or both, thereby providing large capacitance value without any penalty in terms of area or reliability.